Magnetic random access memory and method of reading data from the same

ABSTRACT

In a magnetic random access memory (MRAM), and a method of reading data from the same, the MRAM includes a memory cell having one transistor and one magnetic tunneling junction (MTJ) layer, and a reference cell that is operable for use as a basis when reading data stored in the memory cell, wherein the reference cell includes first and second MTJ layers provided in parallel to each other, and first and second transistors provided in parallel to each other, the first and second transistors being respectively connected in series to the first and second MTJ layers. Alternatively, one transistor having a driving capability corresponding to twice a driving capability of the transistor of the memory cell may be substituted for the first and second transistors of the reference cell.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor memory device and amethod of reading data from the same. More particularly, the presentinvention relates to a magnetic random access memory (MRAM) having areference cell that is capable of maintaining a middle resistancebetween a high resistance and a low resistance of a magnetic tunnelingjunction (MTJ) layer according to changes in a resistance of the MTJlayer caused by an applied voltage and a method of reading data from theMRAM.

2. Description of the Related Art

A magnetic tunneling junction (MTJ) layer of a memory cell of an MRAMhas a resistance that varies according to the direction of magnetizationof a free magnetic film. When the direction of magnetization of the freemagnetic film is the same as the direction of magnetization of a lowermagnetic film formed under a tunneling film, the MTJ layer has a lowresistance R_(L). When the direction of magnetization of the freemagnetic film is not the same as the direction of magnetization of thelower magnetic film formed under the tunneling film, the MTJ layer has ahigh resistance R_(H). Hereinafter, the high resistance is referred toas a maximum resistance of the MTJ layer, and the low resistance isreferred to as a minimum resistance of the MTJ layer.

An MRAM is a memory device that stores data “1” and “0” using the factthat the resistance of the MTJ layer is different according to the stateof magnetization of the free magnetic film. Thus, in order to readinformation recorded in a memory cell, the MRAM includes a referencecell having a resistance (R_(H)+R_(L))/2 (hereinafter, referred to as amiddle resistance) that corresponds to an average resistance of the highresistance R_(H) and the low resistance R_(L) of the MTJ layer. Thereference cell includes a transistor and an MTJ layer connected to thetransistor. The middle resistance of the reference cell is theresistance of the MTJ layer provided in the reference cell.

During operation, the resistances R_(H) and R_(L) of the MTJ layer varyaccording to a voltage applied to the MTJ layer. Thus, as shown in FIG.1, which is a graph of an ideal voltage versus resistance of a magnetictunneling junction (MTJ) layer of a memory cell of an MRAMand an MTJlayer of a reference cell, the resistance of the MTJ layer of thereference cell of the MRAM, which is represented by a solid line, shouldbe constant at a middle resistance (R_(H)+R_(L))/2 between a lowresistance R_(L) (▪) and a high resistance R_(H) (●) of the MTJ layer ofthe memory cell according to a voltage applied to the reference cell.

However, in a case of a reference cell of a conventional MRAM, theabove-described conditions are not satisfied.

FIGS. 2, 5, and 7 are circuit diagrams of a memory cell and a referencecell of a conventional MRAM. FIG. 3 is a graph of voltage versusresistance of an MTJ layer of a memory cell and an MTJ layer of areference cell of the conventional MRAM of FIG. 2. FIG. 4 is a graph ofvoltage versus current of an MTJ layer of a memory cell and an MTJ layerof a reference cell of the conventional MRAM of FIG. 2. FIG. 6 is agraph of voltage versus current of an MTJ layer of a memory cell and anMTJ layer of a reference cell of the conventional MRAM of FIG. 5.

For example, the reference cell of the conventional MRAM includes firstthrough fourth MTJ layers 12, 14, 16, and 18 and a first transistor 10,as shown on the left side of a sensor amplifier (SA) in FIG. 2. A memorycell including a fifth MTJ layer 20 and a second transistor 24 is shownon the right side of the sensor amplifier SA in FIG. 2.

In such a device, a resistance is measured from an MTJ layer.Accordingly, in FIG. 2, each of the MTJ layers is indicated by aresistance. Hereinafter, MTJ layers in all circuits are indicated by aresistance.

The first and second MTJ layers 12 and 14 have a high resistance R^(H)and a low resistance R_(L), respectively. The third and fourth MTJlayers 16 and 18 have a low resistance R_(L) and a high resistanceR_(H), respectively. The first and second MTJ layers 12 and 14 areconnected in series to each other. The third and fourth MTJ layers 16and 18 are also connected in series to each other. The first and secondMTJ layers 12 and 14 and the third and fourth MTJ layers 16 and 18 areconnected in parallel to each other. The first transistor 10 isconnected between the second and fourth MTJ layers 14 and 18.

Referring to FIG. 2, a current I_(s) is supplied to both the referencecell and the memory cell. V_(Ref) and V_(Cell) are a voltage measured inthe reference cell and a voltage measured in the memory cell,respectively. A conventional MRAM including the reference cell and thememory cell shown in FIG. 2 reads information stored in the memory cellusing a difference between the voltages V_(Ref) and V_(Cell).

However, the current I_(s) supplied to the reference cell from a currentsource is divided by two such that a current I_(s)/2 is supplied to eachof the first and second MTJ layers 12 and 14 and the third and fourthMTJ layers 16 and 18. As such, the voltage applied to each MTJ layer ofthe reference cell is about half of the voltage applied to the fifth MTJlayer 20 of the memory cell. For this reason, it is difficult tomaintain the equivalent resistance of the reference cell at(R_(H)+R_(L))/2, as shown in FIG. 3.

Since the equivalent resistance of the reference cell is not maintainedat (R_(H)+R_(L))/2, the voltage V_(Ref) measured in the reference cellhas characteristics shown in FIG. 4.

More specifically, in FIG. 4, symbol ●is a graph showing a voltageV_(Cell,)H measured when the fifth MTJ layer 20 has a high resistance,symbol ▪ is a graph showing a voltage V_(Cell,)L measured when the fifthMTJ layer 20 has a low resistance, and a solid line is a graph showing avoltage V_(Ref) measured in the reference cell. Referring to the graphsin FIG. 4, the voltage V_(Ref) measured in the reference cell isdifferent from (V_(Cell,)H+V_(cell,)L)/2.

Since the voltage measured in the reference cell does not have a middlevalue between a maximum voltage and a minimum voltage measured in thememory cell, in a case of the conventional MRAM having the memory celland the reference cell of FIG. 2, a sensing margin is reduced such thatnoise or malfunction may occur.

The reference cell and the memory cell of FIG. 5 are the same as thereference cell and the memory cell of FIG. 2 in constitution, but avoltage V_(s) instead of a current is applied to the reference cell andthe memory cell. Thus, an MRAM having the reference cell and the memorycell of FIG. 5 reads information recorded in the memory cell using adifference between a current I_(Ref) measured in the reference cell anda current I_(Cell) measured in the memory cell. However, in the case ofthe MRAM of FIG. 5, like the MRAM of FIG. 2, voltages applied to each ofthe first through fourth MTJ layers 12, 14, 16, and 18 of the referencecell are about half of a voltage applied to the fifth MTJ layer 20 ofthe memory cell. Therefore, it is difficult to maintain the equivalentresistance of the reference cell at (R_(H)+R_(L))/2, and it is alsodifficult to maintain the current I_(Ref) measured in the reference cellat a middle value (I_(Cell,)H+I_(Cell,)L)/2 between a maximum currentI_(Cell,)H and a minimum current I_(Cell,)L measured in the memory cell.

Specifically, referring to FIG. 6, symbol ● is a graph showing maximumcurrents I_(Cell,)H measured in the memory cell, symbol ▪ is a graphshowing minimum currents I_(Cell,)L measured in the memory cell, and asolid line is a graph showing a current I_(Ref) measured in thereference cell. Referring to the graphs in FIG. 6, the current I_(Ref)measured in the reference cell is very different from a middle value(I_(Cell,)H+I_(Cell,)L)/2 between the maximum currents I_(Cell,)H andthe minimum currents I_(Cell,)L measured in the memory cell according toan applied voltage.

Thus, in case of the MRAM having the memory cell and the reference cellof FIG. 5, like the MRAM of FIG. 2, a sensing margin is reduced suchthat noise may occur.

FIG. 7 shows an MRAM having a reference cell including sixth and seventhMTJ layers 26 and 28, and the first transistor 10. The sixth MTJ layer26 has a low resistance R_(L), and the seventh MTJ layer 28 has aresistance R_(H) higher than the resistance of the sixth MTJ layer 26.The sixth and seventh MTJ layers 26 and 28 are connected in parallel toeach other, and the first transistor 10 is connected between the sixthand seventh MTJ layers 26 and 28. Here, a voltage 0.5Vs, whichcorresponds to ½ of a voltage V_(s) supplied to the memory cell, isapplied to the reference cell.

In the MRAM shown in FIG. 7, like in the MRAM of FIG. 5, since thevoltage 0.5V_(s) applied to the two MTJ layers 26 and 28 of thereference cell is about half of the voltage V_(s) applied to the fifthMTJ layer 20 of the memory cell, it is difficult to maintain theequivalent resistance of the reference cell at (R_(H)+R_(L))/2. Thus,the current I_(Ref) measured in the reference cell of the MRAM of FIG. 7cannot be maintained at a middle value (I_(Cell,)H+I_(Cell,)L)/² betweenthe maximum current I_(Cell,)H and the minimum current I_(Cell,)Lmeasured in the memory cell, as shown in FIG. 6. For this reason, in thecase of the MRAM of FIG. 7, a sensing margin is reduced such that noiseor malfunction may occur.

SUMMARY OF THE INVENTION

The present invention is therefore directed to a magnetic random accessmemory (MRAM) and a method of reading data from the MRAM, whichsubstantially overcome one or more of the problems due to thelimitations and disadvantages of the related art.

It is a feature of an embodiment of the present invention to provide amagnetic random access memory (MRAM) capable of maintaining theequivalent resistance of a magnetic tunneling junction (MTJ) layer of areference cell at a middle value (R_(H)+R_(L))/2 between a maximumresistance R_(H) and a minimum resistance R_(L) of the MTJ layer of amemory cell even though an applied voltage varies.

It is another feature of an embodiment of the present invention toprovide a method of reading data from the MRAM.

At least one of the above and other features and advantages of thepresent invention may be realized by providing a magnetic random accessmemory (MRAM), including a memory cell having one transistor and onemagnetic tunneling junction (MTJ) layer, and a reference cell that isoperable for use as a basis when reading data stored in the memory cell,wherein the reference cell includes first and second MTJ layers providedin parallel to each other, and first and second transistors provided inparallel to each other, the first and second transistors beingrespectively connected in series to the first and second MTJ layers.

At least one of the above and other features and advantages of thepresent invention may be realized by providing a magnetic random accessmemory (MRAM), including a memory cell having one transistor and onemagnetic tunneling junction (MTJ) layer, and a reference cell that isoperable for use as a basis when reading data stored in the memory cell,wherein the reference cell includes first and second MTJ layers providedin parallel to each other, and a first transistor connected in series tothe first and second MTJ layers, and wherein a driving capability of thefirst transistor of the reference cell is twice a driving capability ofthe transistor of the memory cell.

In either of the above devices, one of the first and second MTJ layersof the reference cell may have a maximum resistance of the MTJ layer ofthe memory cell, and the other of the first and second MTJ layers of thereference cell may have a minimum resistance of the MTJ layer of thememory cell.

At least one of the above and other features and advantages of thepresent invention may be realized by providing a method of reading datafrom a magnetic random access memory (MRAM) including a memory cellhaving one transistor and one magnetic tunneling junction (MTJ) layer,and a reference cell having first and second MTJ layers provided inparallel to each other and first and second transistors provided inparallel to each other, the first and second transistors of thereference cell being connected in series to the first and second MTJlayers, respectively, the method including applying a read current I_(s)to the memory cell, and applying a current 21, corresponding to twicethe read current to the reference cell.

At least one of the above and other features and advantages of thepresent invention may be realized by providing a method of reading datafrom a magnetic random access memory (MRAM) including a memory cellhaving one transistor and one magnetic tunneling junction (MTJ) layer,and a reference cell having first and second MTJ layers connected inparallel to each other and a first transistor which is connected inseries to the first and second MTJ layers, the first transistor having adriving capability corresponding to twice a driving capability of thetransistor of the memory cell, the method including applying a readcurrent I_(s) to the memory cell, and applying a current 2I_(s)corresponding to twice the read current to the reference cell.

According to an embodiment of the present invention, the equivalentresistance of the MTJ layer of the reference cell is maintained at themiddle value between the maximum resistance and the minimum resistanceof the MTJ layer of the memory cell even though the applied voltagevaries, thereby sufficiently providing a sensing margin and preventing amalfunction caused by noise.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present inventionwill become more apparent to those of ordinary skill in the art bydescribing in detail exemplary embodiments thereof with reference to theattached drawings in which:

FIG. 1 is a graph of an ideal voltage versus resistance of a magnetictunneling junction (MTJ) layer of a memory cell of an MRAM and an MTJlayer of a reference cell;

FIGS. 2, 5, and 7 are circuit diagrams of a memory cell and a referencecell of conventional MRAMs;

FIG. 3 is a graph of voltage versus resistance of an MTJ layer of amemory cell and an MTJ layer of a reference cell of the conventionalMRAM of FIG. 2;

FIG. 4 is a graph of voltage versus current of an MTJ layer of a memorycell and an MTJ layer of a reference cell of the conventional MRAM ofFIG. 2;

FIG. 6 is a graph of voltage versus current of an MTJ layer of a memorycell and an MTJ layer of a reference cell of the conventional MRAM ofFIG. 5;

FIG. 8 is a circuit diagram of a memory cell and a reference cell of anMRAM according to an embodiment of the present invention;

FIG. 9 is a graph of voltage versus resistance of an MTJ layer of amemory cell and an MTJ layer of a reference cell of the MRAM of FIG. 8;

FIG. 10 is a graph of voltage versus current of an MTJ layer of a memorycell and an MTJ layer of a reference cell of the MRAM of FIG. 8;

FIG. 11 is a circuit diagram of an array of a memory cell and areference cell of an MRAM according to an embodiment of the presentinvention; and

FIG. 12 is a circuit diagram showing the flow of a current applied to amemory cell and a reference cell corresponding to the memory cell in thememory cell array of FIG. 11.

DETAILED DESCRIPTION OF THE INVENTION

Korean Patent Application No. 10-2003-0100617, filed on Dec. 30, 2003,in the Korean Intellectual Property Office, and entitled: “MagneticRandom Access Memory and Method of Reading Data from the Same,” isincorporated by reference herein in its entirety.

The present invention will now be described more fully hereinafter withreference to the accompanying drawings, in which exemplary embodimentsof the invention are shown. The invention may, however, be embodied indifferent forms and should not be construed as limited to theembodiments set forth herein. Rather, these embodiments are provided sothat this disclosure will be thorough and complete, and will fullyconvey the scope of the invention to those skilled in the art. Likereference numerals refer to like elements throughout.

FIG. 8 is a circuit diagram of a memory cell and a reference cell of anMRAM according to an embodiment of the present invention.

FIG. 8 shows a circuit constitution for a memory cell C2 and a referencecell C1 corresponding to the memory cell C2 of the MRAM according to anembodiment of the present invention. The reference cell is operable foruse as a basis when reading data stored in the memory cell. Referring toFIG. 8, the reference cell Cl includes first and second MTJ layers 50and 52 and first and second transistors 54 and 56. The memory cell C2includes a third MTJ layer 58 and a third transistor 60. The first MTJlayer 50 has a low resistance and may be the same resistance as aminimum resistance of the third MTJ layer 58 of the memory cell C2. Thesecond MTJ layer 52 of the reference cell C1 has a resistance higherthan the resistance of the first MTJ layer 50. The resistance of thesecond MTJ layer 52 may be the same as a maximum resistance of the thirdMTJ layer 58. Alternatively, the above-described relation between thefirst and second MTJ layers 50 and 52 of the reference cell C1 may bereversed. The first and second MTJ layers 50 and 52 of the referencecell C1 are connected in parallel to each other, and the first andsecond transistors 54 and 56 of the reference cell C1 are connected inparallel to each other. The first MTJ layer 50 and the first transistor54 are connected in series to each other. The second MTJ layer 52 andthe second transistor 56 are also connected in series to each other. Thefirst and second transistors 54 and 56 of the reference cell C1 may bethe same as the third transistor 60 of the memory cell C2.

During a read operation, a predetermined read current I_(s) is appliedto the memory cell C2 from a current source and, simultaneously, acurrent 2I_(s) which corresponds to twice the read current I_(s), isapplied to the reference cell C1. Voltages V_(Ref) and V_(Cell) measuredin the reference cell C1 and the memory cell C2, respectively, arecompared with each other to read data stored in the memory cell C2.

In this case, since the first and second MTJ layers 50 and 52 areconnected in parallel to the reference cell C1 as described above, thecurrent 2I_(s) applied to the reference cell C1 is divided so that thesame current as the current I_(s) applied to the memory cell C2 isapplied to each of the first and second MTJ layers 50 and 52. Inaddition, since the first and second transistors 54 and 56, which arethe same as a pass transistor of the memory cell C2, i.e., the thirdtransistor 60, are respectively connected in series to the first andsecond MTJ layers 50 and 52 of the reference cell C1, the voltageapplied to the first and second MTJ layers 50 and 52 of the referencecell C1 is substantially similar to the voltage applied to the third MTJlayer 58 of the memory cell C2. Thus, the equivalent resistance of thereference cell C1 may be maintained at a middle value between a maximumresistance R_(H) and a minimum resistance R_(L) of the third MTJ layer58 of the memory cell C1 even though an applied voltage varies. FIG. 9shows this result in the reference cell C1.

FIG. 9 is a graph of voltage versus resistance of the MTJ layer of thememory cell and the MTJ layers of the reference cell of the MRAM of FIG.8.

In FIG. 9, symbol ● plots changes in the maximum resistance of the thirdMTJ layer 58 of the memory cell C2 according to an applied voltage, andsymbol ▪ plots changes in the minimum resistance of the third MTJ layer58. A solid line shows changes in the resistance measured in thereference cell C1.

Referring to FIG. 9, the resistance measured in the reference cell C1 ismaintained at a middle value between the maximum resistance and theminimum resistance of the third MTJ layer 58 of the memory cell C2, eventhough the applied voltage varies.

Since the resistance of the reference cell C1 is maintained at themiddle value between the maximum resistance and the minimum resistanceof the memory cell C2, the voltage V_(Ref) of the reference cell C1 canbe constantly maintained at a middle value (V_(Cell,)H+V_(Cell,)L)/2between the maximum voltage V_(Cell,)H and the minimum voltageV_(Cell,)L of the memory cell C2 even though the applied voltage varies.FIG. 10 shows this result.

FIG. 10 is a graph of voltage versus current of the MTJ layer of thememory cell and the MTJ layers of the reference cell of the MRAM of FIG.8.

In FIG. 10, symbol ● plots changes in the maximum resistance V_(Cell,)Hof the memory cell C2 according to an applied voltage, and symbol ▪plots changes in the minimum resistance V_(Cell,)L of the memory cell C2according to the applied voltage. A solid line shows changes in theresistance measured in the reference cell C1 according to the appliedvoltage.

Referring to FIG. 10, it may be seen that the voltage of the referencecell C1 is a middle value between the maximum voltage V_(Cell,)H and theminimum voltage V_(Cell,)L of the memory cell C2 at any applied voltage.Based on this result, by using an MRAM according to an embodiment of thepresent invention, a sufficient sensing margin can be obtained so thatdata can be stably read without malfunction.

Alternatively, a reference cell according to an alternative embodimentof the present invention (hereinafter “the alternative reference cell”)may substitute one transistor for the first and second transistors 54and 56 in the reference cell C1 of FIG. 8. In this case, the onetransistor is a pass transistor. Since a current that passes through twoMTJ layers 50 and 52 connected in parallel passes through the onesubstituted transistor, the driving capability of the one substitutedtransistor may be twice the driving capability of the third transistor60 in the memory cell C2.

In a case of an MRAM including the alternative reference cell, a processof reading data from the memory cell C2 is the same as a process to beperformed by the MRAM including the reference cell C1.

As a further alternative, the position of each MTJ layer and theposition of each transistor may be reversed from the reference cell C1of FIG. 8.

FIG. 11 is a circuit diagram of an array of a memory cell and areference cell of an MRAM according to an embodiment of the presentinvention. FIG. 12 is a circuit diagram showing the flow of a currentapplied to a memory cell and a reference cell corresponding to thememory cell in a memory cell array of FIG. 11.

FIG. 11 shows a cell array of an MRAM including the above-describedalternative reference cell and memory cell. In FIG. 11, a reference cellcolumn 100 includes a plurality of alternative reference cells. Onereference cell column 100 is disposed in each memory cell block. Acurrent 2I_(s), which corresponds to twice a current I_(s) applied to amemory cell column, is applied to the reference cell column 100. Onecolumn of a memory cell block is selected by column select transistorsY0, Y1, Y2, and Y3 disposed under the cell array and is compared withthe reference cell column 100. A digit line DL is used in recording datain an MTJ layer of the memory cell. When a current is applied to thedigit line DL, a ground line GL is floated so that a current does notflow through a pass transistor connected to the MTJ layer.

FIG. 12 shows a path through which a current applied to a correspondingmemory cell and the reference cell column 100 flows, so as to read datastored in a memory cell connected to a predetermined selected word line,e.g., a first word line WL0, of the MRAM array of FIG. 11. In FIG. 12, aleft circuit is a memory cell of a memory cell column to which a readcurrent I_(s) is applied and which is connected to the first word lineWL0, and a right circuit is the alternative reference cell of thereference cell column 100 to which a current 2I_(s) corresponding totwice the read current I_(s) is applied and which is connected to thefirst word line WL0.

Referring to FIG. 12, since word lines other than the first word lineWL0 are in an “off” state, the read current I_(s) applied to the memorycell connected to the first word line WL0 passes through an MTJ layer102 of the memory cell and a transistor MT1 connected in series to theMTJ layer 102 and flows through a ground line GL connected to thetransistor MT1. The current 2I_(s) applied to the reference cell column100 is divided into two at a first node N1 so that first and secondcurrents I1 _(s) and I2 _(s) are applied to two parallel-connected MTJlayers 106 and 108. The first and second currents I1 ^(s) and I2 _(s)have the same value. The first current I2 _(s) applied to the MTJ layer106 connected to a transistor CT1 flows through the ground line GL viathe transistor CT1 in an “on” state. The second current I2 _(s) passesthrough a second node N2, an MTJ layer 108 connected in series to atransistor CT2 in an off state connected to a second word line WL1, athird node N3, which is a connection point between the transistor CT2and the MTJ layer 108, a fourth node N4, which is a connection pointbetween the transistor CT1 and the MTJ layer 106, and the transistor CT1connected to the first word line WL0 and flows through the ground lineGL.

Since the current applied to the alternative reference cell passesthrough the two MTJ layers 106 and 108 that are connected in parallel toeach other and then the transistor CT1, the driving capability of thetransistor CT1 of the alternative reference cell may be twice thedriving capability of a transistor MT1 of the memory cell.

In FIG. 12, a transistor of the memory cell MT2 and a transistor of thereference cell CT2 according to the alternative embodiment are connectedto the second word line WL1. An MTJ layer 104 of the memory cell isconnected to the second word line WL1.

As described above, the reference cell of the MRAM according to thepresent invention includes an MTJ layer having a maximum resistance ofan MTJ layer of a memory cell and an MTJ layer having a minimumresistance of an MTJ layer of the memory cell, which are connected inparallel to each other, and two pass transistors connected in series toeach MTJ layer and having the same driving capability as the drivingcapability of a pass transistor of the memory cell. In this case, thetwo pass transistors of the reference cell may be substituted for onepass transistor having a driving capability corresponding to twice adriving capability of the pass transistor of the memory cell. In thecase of an MRAM according to an embodiment of the present invention, thesame current as the current applied to the MTJ layer of the memory cellis applied to each MTJ layer of the reference cell. Thus, the equivalentresistance measured in the reference cell is a middle value between themaximum resistance and the minimum resistance measured in the memorycell. In addition, a voltage V_(Ref) measured in the reference cell hasa middle value between a maximum voltage V_(Cell,)H and a minimumvoltage V_(Cell,)L measured in the memory cell even though the appliedvoltage varies. Thus, in the case of the MRAM according to the presentinvention, a sufficient sensing margin can be obtained, and malfunctioncaused by noise can be prevented.

Exemplary embodiments of the present invention have been disclosedherein and, although specific terms are employed, they are used and areto be interpreted in a generic and descriptive sense only and not forpurpose of limitation. Accordingly, it will be understood by those ofordinary skill in the art that various changes in form and details maybe made without departing from the spirit and scope of the presentinvention as set forth in the following claims.

1. A magnetic random access memory (MRAM), comprising: a memory cellhaving one transistor and one magnetic tunneling junction (MTJ) layer;and a reference cell that is operable for use as a basis when readingdata stored in the memory cell, wherein the reference cell includesfirst and second MTJ layers provided in parallel to each other; andfirst and second transistors provided in parallel to each other, thefirst and second transistors being respectively connected in series tothe first and second MTJ layers.
 2. The MRAM as claimed in claim 1,wherein one of the first and second MTJ layers of the reference cell hasa maximum resistance of the MTJ layer of the memory cell, and the otherof the first and second MTJ layers of the reference cell has a minimumresistance of the MTJ layer of the memory cell.
 3. A magnetic randomaccess memory (MRAM), comprising: a memory cell having one transistorand one magnetic tunneling junction (MTJ) layer; and a reference cellthat is operable for use as a basis when reading data stored in thememory cell, wherein the reference cell includes first and second MTJlayers provided in parallel to each other; and a first transistorconnected in series to the first and second MTJ layers, and wherein adriving capability of the first transistor of the reference cell istwice a driving capability of the transistor of the memory cell.
 4. TheMRAM as claimed in claim 3, wherein one of the first and second MTJlayers of the reference cell has a maximum resistance of the MTJ layerof the memory cell, and the other of the first and second MTJ layers ofthe reference cell has a minimum resistance of the MTJ layer of thememory cell.
 5. A method of reading data from a magnetic random accessmemory (MRAM) including a memory cell having one transistor and onemagnetic tunneling junction (MTJ) layer, and a reference cell havingfirst and second MTJ layers provided in parallel to each other and firstand second transistors provided in parallel to each other, the first andsecond transistors of the reference cell being connected in series tothe first and second MTJ layers, respectively, the method comprising:applying a read current I_(s) to the memory cell; and applying a current2I_(s) corresponding to twice the read current to the reference cell. 6.A method of reading data from a magnetic random access memory (MRAM)including a memory cell having one transistor and one magnetic tunnelingjunction (MTJ) layer, and a reference cell having first and second MTJlayers connected in parallel to each other and a first transistor whichis connected in series to the first and second MTJ layers, the firsttransistor having a driving capability corresponding to twice a drivingcapability of the transistor of the memory cell, the method comprising:applying a read current I_(s) to the memory cell; and applying a current2I_(s) corresponding to twice the read current to the reference cell.